1. Field of the Invention
The present invention relates a reference voltage supply circuit which is used as a power supply circuit for an integrated circuit or such and particularly, to a reference voltage supply circuit, dispersion of whose reference output voltage caused by a fabrication process or such is suppressed.
2. Description of the Prior Art
When a reference voltage supply circuit is provided in a semiconductor device, a reference voltage supply circuit has in many cases been fabricated by a bipolar process, which is widely used for fabrication of an analogue circuit since there is a necessity of increasing relative precision of elements and precision in absolute value of a resistor. The reason why is also that since it is an analogue circuit that requires a reference voltage supply circuit, there is no other choice but to employ a bipolar process.
In recent years, an analogue circuit has been built even in a CMOS process which is used for a digital circuit in company with progress in integration of circuitry. Hence, there arises a necessity for a reference voltage supply circuit to be incorporated in a CMOS process.
FIG. 1 is a circuit diagram showing a conventional reference voltage supply circuit. The reference voltage supply circuit comprises two PNP transistors Q31 and Q32 whose collectors and bases are grounded. Resistor elements RE33 and RE32 are serially connected to the emitter of the transistor Q32 in that order. Further, a resistor element RE31 is connected to the emitter of the transistor Q31. The input terminal of an amplifier AMP31 is connected to a connection point between the emitter of the transistor Q31 and the resistor element RE31 and a connection point between the resistor elements RE32 and RE33. The resistor elements RE31 and RE32 are connected to each other and the connection point is connected to the output terminal of the amplifier AMP31. A voltage output terminal OUT31 is connected to the output terminal of the amplifier AMP31. In the mean time, the amplifier AMP31 includes plural elements such as a CMOS transistor.
A method to construct a reference voltage supply circuit as described above using a CMOS process is described, for example, in a reference xe2x80x9cA Precision Curvature-Compensated CMOS Bandgap Reference:xe2x80x9d p634-643 of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, No. 6, DECEMBER, 1983.
FIG. 2 is a schematic sectional view showing a resistor and a PNP transistor provided in a conventional reference voltage supply circuit. A resistor and a PNP transistor provided in a conventional circuit are fabricated at the surface of a Pxe2x88x92-substrate 100, as shown in FIG. 2. Two Nxe2x88x92-wells 101a and 101b are selectively formed at the surface of a Pxe2x88x92-substrate 100. Further, an N+-diffused layer 102a and a P+-diffused layer 102b are formed at a surface of the Nxe2x88x92-well 101a. Two terminals 130b and 103c are connected to the P+-diffused layer 102b. A well bias terminal 103a is connected to the N+-diffused layer 102a. In such a manner, the resistor element 104 is constructed.
On the other hand, a P+-diffused layer 106 and an N+-diffused layer 105 are formed at a surface of the Nxe2x88x92-well 101b. An emitter terminal 109 is connected to the P+-diffused layer 106 and a base terminal 108 is connected to the N+-diffused layer 105. Further, a P+-diffused layer 107 is formed at the surface of a Pxe2x88x92-substrate 100 at a position so that the N+-diffused layer 105 is placed between the P+-diffused layers 106 and 107. A collector terminal 110 is connected to the P+-diffused layer 107. In such a manner, a PNP transistor 111 is constructed.
A process for fabrication of a reference voltage supply circuit including a resistor and a transistor with such constructions has easily been realized in a process for fabrication of a digital circuit including a CMOS transistor which is provided in the amplifier AMP31.
However, in a recent fabrication process, in which a gate length of a CMOS transistor is equal to or less than 0.5 xcexcm, there arises a necessity to reduce a signal delay in a CMOS digital circuit as much as possible. Hence, a resistance lowering technique called Salicide (self aligned silicide) has been applied to electrodes for the gate, source and drain of a MOS transistor.
As a result, a sheet resistance xcfx81S of a resistor element with a resistor of the same width and length is on the order of 10 xcexa9/xe2x96xa1 and magnitudes of a sheet resistance xcfx81 S of electrodes for a gate, source and drain have a tendency to further decrease together with future progress in a CMOS transistor process.
On the other hand, a desired value of resistance of a resistor element provided in a reference voltage supply circuit is a very large value in the range of some tens of kxcexa9 to several Mxcexa9. When a large current flows through the base, emitter or collector of a bipolar transistor provided in a reference voltage supply circuit, a voltage drop in diffused layers of the collector, emitter and base including those of electrodes cannot be neglected, if the resistance of the resistor element is lower. That eventually causes undesirable shift from ideal electrical characteristics of a bipolar transistor. Therefore, a current is desired to be small.
In order to fabricate a resistor with a resistance in the range of some tens of kxcexa9 to several Mxcexa9 in a recent CMOS semiconductor fabrication process using a Salicide technique, when the resistor is fabricated using an electrode material for a gate, source or drain having a small resistance per a unit area, a length of the resistor is required to be very long on a semiconductor substrate. For example, if a resistor with a resistance of 20 kxcexa9 and a width of 2 xcexcm is fabricated using a material of xcfx81S =10 xcexa9/xe2x96xa1, a necessary length is as long as 4 mm. That is, a large area is consumed for a resistor element. However, since a fabrication cost per a unit area of a recent CMOS transistor is high, a low resistor material is not suitable for the gate, source or drain of a CMOS transistor.
In such circumstances, there is available a method in which, in order that a resistance of a resistor element is prevented from being lowered without increase in the number of fabrication process steps, an LDD (Lightly Doped Drain) diffused layer is used as a resistor element instead of the resistor shown in FIG. 2. The LDD diffused layer is introduced in a recent CMOS circuit in order to improve an ability to endure ESD (electrostatic destruction) by preventing local intensification of an electric field in the vicinity of the drain. An LDD diffused layer is formed as a shallow layer at the surface of a semiconductor substrate in a region in which the source and drain are fabricated. A sheet resistance xcfx81S of the LDD diffused layer is several kxcexa9 and the highest value encountered in a recent semiconductor fabrication process.
However, an LDD diffused layer is a very thin layer formed at the surface of a semiconductor substrate and fabricated in an early stage of a fabrication process. Therefore, the LDD diffusion layer has a fault that resistance dispersion thereof becomes large compared with other resistors by influences of surface treatments of the semiconductor substrate after the formation of the layer in the fabrication process such as an etching step. As a result, dispersion of an output voltage in absolute value of a reference voltage supply circuit is larger.
Further, there is also available a method in which, in order that a resistor material with a high sheet resistance is built in a different way, the gate electrode formed on a semiconductor substrate is protected so as not to be transformed to a Salicide and thereby a high resistance is secured. FIG. 3 is a schematic sectional view showing a resistor and a PNP transistor which are provided in another conventional reference voltage supply circuit.
A resistor and a PNP transistor provided in another conventional reference voltage supply circuit in which the gate electrode is used as a resistor element are formed on the surface of a Pxe2x88x92-substrate 120, as shown in FIG. 3. An Nxe2x88x92-well 121 is selectively formed at the surface of the P+-substrate 120. Further, a gate electrode 122 made of polysilicon is selectively formed on a region of the P+-substrate 120 in which the Nxe2x88x92-well 121 is not formed. Two terminals 123a and 123b are connected to the gate electrode 122. In such a manner, a resistor element 124 is constructed.
On the other hand, a P+-diffused layer 126 and an N+-diffused layer 125 are formed at the surface of the Nxe2x88x92-well 121. An emitter terminal 129 is connected to the P30 -diffused layer 126 and a base terminal 128 is connected to the N+-diffused layer 125. Further, a P+-diffused layer 127 is formed at the surface of the Pxe2x88x92-substrate 120 so that the N+-diffused layer 125 is placed between the P+-diffused layers 126 and 127. A collector terminal 130 is connected to the P+-diffused layer 127. In such a manner, a PNP transistor 131 is constructed.
However, in order to fabricate a high resistivity polysilicon resistor (gate electrode 122) showing such a high sheet resistance xcfx81S, at least one dedicated mask is required. Hence, there arises a problem that a cost is raised due to increase in number of fabrication steps due to this requirement.
Further, when a change to a resistor made of a LDD diffused layer and use of a polysilicon resistor are effected, there arises a fault that dispersion in absolute value of an output voltage of a reference voltage supply circuit is large compared with the conventional technique in FIG. 2. This is because, since a material different from a semiconductor material constituting the base, emitter or collector of a PNP transistor is used, a shift in electric characteristics of a PNP transistor and dispersion of a resistor element independently act on dispersion of an output voltage in absolute value of a reference voltage supply circuit unfavorably.
Therefore, as a method to solve a fault that dispersion characteristics of a resistor and a PNP transistor independently affect dispersion of output voltage, an example in which an N type semiconductor substrate is adopted is described in xe2x80x9cA Precision CMOS Bandgap Referencexe2x80x9d: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, No. 6, DECEMBER 1984, P1014-1021.
FIG. 4A is a schematic sectional view showing a CMOS transistor provided in a conventional reference voltage supply circuit which is described in the prior art reference and FIG. 4B is a schematic sectional view showing a resistor and a bipolar transistor provided in the conventional reference voltage supply circuit.
A CMOS transistor provided in the conventional reference voltage supply circuit is formed at the surface of an Nxe2x88x92-substrate 141. A Pxe2x88x92-well 142 is selectively formed at the surface of the Nxe2x88x92-substrate 141. Further, two P+-diffused layers 143a and 143b are formed at the surface of the Pxe2x88x92-well 142 and two N+-diffused layers 144a and 144b are formed between P+-diffused layers 143a and 143b. A gate insulating film (not shown) is formed on the Pxe2x88x92-well 142 between the N+-diffused layers 144a and 144b, and a gate electrode 145 is formed on the gate insulating film. A well bias terminal 146 is connected to the P+-diffused layers 143a and 143b. A drain terminal 147 is connected to the N+-diffused layer 144a. A source terminal 148 is connected to the N+-diffused layer 144b. A gate electrode terminal 149 is connected to the gate electrode 145.
Further, two N+-diffused layers 151a and 151b are formed at the surface of the Nxe2x88x92-substrate 141 in a region in which the Pxe2x88x92-well 142 is not formed and two P+-diffused layers 152a and 152b are formed between N+-diffused layers 151a and 151b. Further, a gate insulating film (not shown) is formed on the Nxe2x88x92-substrate 141 between the P+-diffused layers 152a and 152b and a gate electrode 153 is formed on the gate insulating film. A substrate bias terminal 154 is connected to N+-diffused layers 151a and 151b. A drain terminal 155 is connected to the P+-diffused layer 152a. A source terminal 156 is connected to the P+-diffused layer 152b. A gate electrode terminal 157 is connected to the gate electrode 153.
On the other hand, a resistor and a bipolar transistor provided in a conventional reference voltage supply circuit are formed at the surface of an Nxe2x88x92-substrate 141, as shown in FIG. 4B. Two Pxe2x88x92-wells 161a and 161b are selectively formed at the surface of the Nxe2x88x92-substrate 141. Further, two P+-diffused layers 162a and 162b are formed at the surface of the Pxe2x88x92-well 161a and terminals 163a and 163b are respectively connected to the P+-diffused layers 162a and 162b. In such a manner, a resistor element 164 is constructed.
A P+-diffused layer 165 and an N+-diffused layer 166 are formed at the surface of the Pxe2x88x92-well 161b, a base terminal 168 is connected to the P+-diffused layer 165 and an emitter terminal 169 is connected to the N+-diffused layer 166. Further, an N+-diffused layer 167 is formed at a position at the surface of the Nxe2x88x92-substrate 141 so that the P+-diffused layer 165 is placed between the N+-diffused layers 166 and 167. A collector terminal 170 is connected to the N+-diffused layer 167. In such a manner, a transistor 171 is constructed.
Dispersion in characteristics of the Pxe2x88x92-well 161a formed at the surface of the Nxe2x88x92-substrate 141 is small compared with other regions. Hence, a reference voltage supply circuit constructed as described above has small dispersion of an output voltage in absolute value.
However, in formation of a Pxe2x88x92-well, B+ ion (boron ion) implantation, is used. A scattering distance of boron ions is comparatively large into a semiconductor substrate. This is because boron has a small mass number and is a low atomic weight material.
Further, since ions with high energy are implanted in a silicon semiconductor substrate in an ion implantation process of impurities, crystal defects are easy to be produced in the vicinity of the surface of an N-type semiconductor substrate. Therefore, an annealing process, in which a semiconductor substrate is heated, is necessary after ion implantation in order to remove the crystal defects. Impurity ions in a semiconductor substrate have a characteristic that the impurity ions diffuse from a site with a high concentration to a site with a low concentration under heating. A thermal diffusion length of a boron ion is several times as high as that of P (phosphorus) which is impurities in an N-type semiconductor device. In an ion implantation process, an impurity concentration and a size of a well can be controlled with high precision by monitoring a current, an applied voltage and time. However, when an annealing process is long or a heating temperature is high after the ion implantation, a resistor of a Pxe2x88x92-well has a larger dispersion than a resistor of an Nxe2x88x92-well.
Further, in the case where a CMOS circuit is fabricated with an N-type semiconductor substrate, a negative power supply is required from a view point of an electric circuit and thereby there arises a problem that an output voltage of a reference voltage supply circuit is negative. That is, such a problem is unfavorable for actual products in which a positive power supply is widely adopted.
Further a reference voltage supply circuit in which a MOS transistor is used instead of a parasitic bipolar transistor has been proposed (Japanese Patent Application Laid-Open No. Hei 6-204838). Since a MOS transistor is used instead of a parasitic bipolar transistor in the conventional reference voltage supply circuit described in the official gazette, the reference voltage supply circuit can be fabricated together with a CMOS transistor. Further dispersion of an output voltage due to a change in temperature and such is suppressed. However, an effect to suppress the dispersion is insufficient.
Besides, a generation apparatus for a threshold whose object is to sufficiently supply a charge current and discharge current to bit lines of memory arrays is proposed (Japanese Patent Application Laid-Open No. Hei 3-30186). However, while a circuit for achieving the object and its operation are disclosed in the official gazette and the object may thereby be achieved, dispersion of an output voltage cannot be suppressed by the apparatus.
It is an object of the present invention to provide a reference voltage supply circuit which not only can be fabricated without increase in fabrication cost but can also supply a reference output voltage with suppressed dispersion in a stable manner even if a sheet resistance is decreased.
According to one aspect of the present invention, a reference voltage supply circuit may comprise a P-type semiconductor substrate, a PNP transistor having an N-type well for a base formed at the surface of the P-type semiconductor substrate, and a resistor element connected to an emitter of the PNP transistor and having an N-type well for a resistor at the surface of the P-type semiconductor substrate. The N-type well for a resistor may be fabricated at the same time as when the N-type well for a base is fabricated.
In one aspect of the present invention, since the N-type well for a base and the N-type well for a resistor are simultaneously fabricated, that is since both are fabricated with the same material, dispersion of a reference output voltage which is caused by a fabrication process and such is greatly suppressed. The reason why is that thermal diffusion of impurities, for example phosphorus ions, which is used in formation of an N-type well is small.
The PNP transistor may comprise a P-type diffused layer for an emitter electrode formed at a surface of the N-type well for a base, an N-type diffused layer for a base electrode formed at the surface of the N-type well for a base, and a P-type diffused layer for a collector electrode which is fabricated at the surface of the P-type semiconductor substrate at the same time as when the P-type diffused layer for an emitter electrode is fabricated. An impurity concentration in the N-type diffused layer for a base electrode may be higher than that in the N-type well for a base. The resistor element may comprise N-type diffused layers each for a resistor electrode which are fabricated at a surface of the N-type well for a resistor at the same time as when the N-type diffused layer for a base electrode is fabricated.
Further, the resistor element preferably comprises a P-type diffused layer for bias formed between the N-type diffused layers each for a resistor electrode.
When a bias voltage is applied to the P-type diffused layer for bias, a depletion layer is produced in the vicinity of the interface between the P-type diffused layer for bias and the N-type well for a resistor. With the depletion layer produced, a sectional area of a region which acts as a resistor of the N-type well is decreased to increase a resistance. Accordingly, even if a resistance itself of the N-type well for a resistor is designed to be decreased, a sufficient resistance can be secured by controlling a bias voltage.
The P-type diffused layer for bias may be fabricated at the same time as when the P-type diffused layer for an emitter electrode is fabricated.
The reference voltage supply circuit may further comprise a P-channel MOS transistor which includes an N-type well for a MOS transistor and P-type diffused layers for a source and a drain. The N-type well for a MOS transistor is fabricated at the surface of the P-type semiconductor substrate at the same time as when the N-type well for a base is fabricated. The P-type diffused layers for a source and a drain are fabricated at a surface of the N-type well for a MOS transistor at the same time as when the P-type diffused layer for an emitter electrode is fabricated.
According to another aspect of the present invention, a reference voltage supply circuit may comprise an N-type semiconductor substrate, an NPN transistor, and a resistor element connected to an emitter of the NPN transistor. The NPN transistor may include a P-type well for a base formed at a surface of the N-type semiconductor substrate, an N-type diffused layer for an emitter electrode formed at a surface of the P-type well for a base, a P-type diffused layer for a base electrode formed at the surface of said P-type well for a base, and an N-type diffused layer for a collector electrode. An impurity concentration in the P-type diffused layer for a base electrode may be higher than that in the P-type well for a base. An N-type diffused layer for a collector electrode is fabricated at the surface of the N-type semiconductor substrate at the same time as when the N-type diffused layer for an emitter electrode is fabricated. The resistor element may include a P-type well for a resistor, P-type diffused layers each for a resistor electrode, and an N-type diffused layer for bias formed between the P-type diffused layers each for a resistor electrode. The P-type well for a resistor is fabricated at the surface of the N-type semiconductor substrate at the same time as when the P-type well for a base is fabricated. The P-type diffused layers each for a resistor electrode are fabricated at a surface of the P-type well for a resistor at the same time as when said N-type diffused layer for an emitter electrode is fabricated.
In the other aspect of the present invention, when a bias voltage is applied to the N-type diffused layer for bias, a depletion layer is produced in the vicinity of the interface between the N-type diffused layer for bias and the P-type well for a resistor. With the depletion layer produced, a sectional area of a region which acts as a resistor of the P-type well for a resistor is decreased to increase a resistance. Accordingly, even if a resistance itself of the P-type well for a resistor is designed to be decreased, a sufficient resistance can be secured by controlling a bias voltage.
The N-type diffused layer for bias is preferably fabricated at the same time as when the N-type diffused layer for an emitter electrode is fabricated.
The reference voltage supply circuit may further comprise an N-channel MOS transistor which includes a P-type well for a MOS transistor and N-type diffused layers for a source and a drain. The P-type well for a MOS transistor is fabricated at the surface of the N-type semiconductor substrate at the same time as when the P-type well for a base is fabricated. The N-type diffused layers for a source and a drain are fabricated at a surface of the P-type well for a MOS transistor at the same time as when the N-type diffused layer for an emitter electrode is fabricated.
In such a manner, according to the present invention, since a well for a base and a well for a resistor are fabricated at the same time, that is since both are fabricated with the same material, dispersion of a reference output voltage which is caused by a fabrication process and such is greatly suppressed.
Further, since a bipolar transistor and a resistor element can be fabricated at the same time as when a process which is used for fabrication of a CMOS transistor provided in a conventional reference voltage supply circuit is performed, fabrication steps are prevented from increasing in number.